1. Technical Field
The invention relates to an analog-to-digital converting technique, which may reduce conversion errors resulting from variations of process, voltage, temperature, or noise.
2. Description of Related Art
Information in digital format is common nowadays, which is convenient for information storing or processing. For example, a video electronic device needs to convert an analog signal to a digital signal for subsequent processing. Therefore, an analog-to-digital converting circuit is an essential circuit in a digitalizing electronic device.
Nevertheless, as a video analog-to-digital converter (ADC) is easily affected by variations of process (P), voltage (V), temperature (T) and noise, a discrepancy or error may occur in an ADC output code.
FIG. 1 is a schematic block drawing illustrating a conventional analog-to-digital converting circuit. With reference to FIG. 1, in terms of operation mechanism of an analog-to-digital converting circuit, a reference circuit 50 is needed to generate a required “working voltage” and “working current” to each of ADC 100, three for example, which are numbered as ADC1-ADC3.
In each of the ADC 100, a gain block 102 generates a required ADC input range voltage signal 104 to an ADC core unit 118, so as to control the range to be digitalized.
Each of the ADC 100 also includes an offset block 108, which connects to the gain block 102 to receive another voltage signal 106 outputted from the gain block 102, and generates an offset voltage signal, which is represented by ADC_VIM; the offset voltage signal is regulated by an external regulator 110, and a voltage value after regulation is represented by Voffset
Each of the ADC 100 also includes a clamp voltage block 112. An output generated by the gain block 102 to the offset block 108 is also inputted to the clamp voltage block 112, so as to generate a clamp voltage signal required for clamping. A multiplexer (MUX) 114 receives the clamp voltage signal and a ground voltage and outputs a clamp voltage Vclamp, which is also regulated by an external capacitor 120.
Each of the ADC 100 also receives an inputted analog voltage signal Vin, which is inputted to the internal through an external capacitor 122. Also, through a switch 124, the clamp voltage Vclamp outputted from the MUX 114 adds a DC level to each input signal, and a data voltage signal is thus generated, which is represented by ADC_VIP.
Each of the ADC 100 also includes a DC buffer 116, which receives the data voltage signal ADC_VIP and the offset voltage signal ADC_VIM. The voltage signals of ADC_VIP and ADC_VIM, after being inputted to the DC buffer 116, are outputted to the ADC core unit 118 through the DC buffer 116, and through the algorithm thereof, different sizes of analog voltage signal Vin are generated, and converted digital codes are outputted. As such, the analog voltage signal Vin may be a gray level signal in an RGB (red, green, blue) color system or a color signal in a YPbPr system.
In the above-mentioned ADC 100, the working voltage or working current generated by the reference circuit may be affected by variations of process, voltage, temperature and noise. Moreover, the voltage signals of ADC_VIP and ADC_VIM, and the ADC input range voltage signal may also vary. If the differences among these signals are not consistent, incorrect digital codes may be generated.
Further researches are necessary for improving the correctness of the digital code outputted from the ADC 100.